Hard IP, an Undervalued Resource

By Mahendra Jain

Hard intellectual property (IP) may be the most undervalued and under utilized resource that the electronics and semiconductor industry has available today.

Hard IP -- designs represented as mask layouts -- offers an attractive return on investment for system-on-a-chip (SOC) design and implementation. And yet, most of the available hard IP is used only once for various reasons -- lack of designer expertise, a viable design environment, the focus of the electronic design automation (EDA) industry on front-end design methodologies.

Reusing legacy data in the form of hard IP could be the viable, practical solution to managing and implementing better, cheaper and faster designs.

Deep submicron semiconductor technology is making SOC design a reality. The industry has concluded that in order to implement this design methodology, it needs to reuse existing designs or, more accurately, blocks of preverified and synthesized IP, also called soft IP.

Interesting conclusion, though we at Sagantec believe it's the wrong one. The industry is clearly on the right path, but much more focus must be placed on devising solutions to effectively reuse physical layout files, or hard IP.

The industry stubbornly stays focused on soft IP because there's a perception that it's easier to modify than hard IP. Until recently, EDA software suppliers focused the majority of their R&D efforts on logic design challenges, not physical design layout. That's why traditional EDA methodologies cannot accommodate new submicron process technologies.

Soft IP is available as a netlist or a hardware description language (HDL) description. As preverified and synthesized software blocks, it offers flexibility, but it needs to be functionally verified. It is easily modified, but requires re-placement and re-routing at the layout level, the equivalent of a complete redesign and a new silicon verification cycle.

In contrast, hard IP offers far greater returns for SOC design and implementation. It offers designers the ability to optimize the design directly at the layout level. Hard IP reuse can accelerate a product's time-to-market by migrating a cell library or a block from an old design into a new design.

Reuse of hard IP is accomplished through process migration. Migrating a layout means adapting it to newer process design rules. Layout designs are migrated for reuse, for second sourcing, and to reduce silicon cost by migrating to a process with smaller design rules. Migration for second sourcing is popular among fabless semiconductor companies that try not to be dependent on one silicon vendor.

One effective method for reusing existing hard IP is layout-to-layout migration. This method does not require a major change in the design methodology and is an easier way to implement a reuse methodology. It also can be used for hard IP not created with reuse in mind. This method is useful for reusing components and can be applied to optimize performance and power in new designs.

As SOC design becomes more mainstream, the focus will naturally shift to hard IP reuse. Companies must be prepared to change their business model, and many have begun to do so. They're creating organizations to coordinate and reuse existing hard IP, and develop new hard IP with the goal of reuse. Designers are now re-learning the way they do integrated circuit design to leverage the integration capabilities offered by the deep submicron semiconductor technology.

To implement a design reuse strategy, the industry need look no further than the massive amount of legacy data that takes the form of hard IP. It will find unquestionably that it serves as a practical solution to SOC design.