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Hard IP offers some hard-core values

Chris W. H. Strolenberg
Product Architect
Sagantec
Email: chris@sagantec.nl
Web Site: http://www.sagantec.com

Design reuse is a must today for efficient implementation of system on chip (SOC) designs. According to a recent study conducted by Collett International, design teams can save an average of 62 percent of the effort that they would otherwise expend in the absence of reusing previously designed blocks. Both hard IP –– design represented as mask layout–– and soft IP –– design represented as register transfer level (RTL) code or a netlist –– are being reused.

The reuse of hard IP is growing because semiconductor companies that own majority of the hard IP are realizing the value it offers. Hard IP accounts for a sizable portion of IP reuse for current SOC designs. Industry estimates place it at 26 percent of the total amount of reused IP.

Reusing existing hard IP is becoming a fact of life for design teams because demand for more complex designs is having an effect on project schedules. Product life cycles are becoming shorter, demanding shorter design cycles for each new product generation.

The hard IP reuse methodology enables designers to efficiently implement SOCs and permits them to optimize that IP for performance or power. The same methodology can also be used for new designs being created. With deep submicron (DSM) designs, timing closure is becoming a bottleneck. A hard IP reuse methodology can be applied to optimize hard IP being designed to achieve rapid timing closure. Hard IP optimization, therefore, is an important consideration for both reuse and design.

Semiconductor processes are also facing a shorter life span with each new generation –– as short as 18 months for 0.18-m processes. Deep submicron processes are making the final mask design stage more critical and time consuming, due to increased parasitic effects that influence timing and functionality. This forces design teams to implement some form of process independence into their design flow.

By definition, hard IP reuse involves being able to take a mask-level designed block, in GDSII format, and to migrate that to a different process. Since this method involves a polygon-level re-layout, it imposes inherent demands on the similarity between the processes concerned –– migration from a GaAs to a CMOS processes is generally not possible, for example.

What makes hard IP reuse an attractive method:

A hard IP block has already been proven and verified in silicon, making its reuse more reliable.

>From an IP user/IP provider perspective, a hard IP block has greater value since the block is designed up to mask layout level and is verified in silicon. The IP user is saved from running layout on blocks where internals are not known. IP in hard form is better protected from illegal reuse. Reuse of hard IP allows the original software created for the design to be reused without modification. Existing software can be an even larger amount of IP compared to the integrated circuit (IC) itself. Hard IP reused in conjunction with circuit optimization and automatic layout migration software allows for optimization for performance and power consumption simultaneously. New derivative products can be easily created by adjusting transistor sizes for enhanced performance.

Hard IP Reuse Methodologies

Various methods exist for designers to reuse hard IP. Optical shrink, polygon level re-layout and layout migration are the most well known.

The optical shrink technique is successful and reliable. Despite the inherent area penalty, a shrink can be reasonably efficient, provided that process design rules were optimized to allow for a good shrink-path. With DSM processes, however, shrinking is hardly an alternative. A nonlinear re-layout of the design is the required approach.

Polygon level re-layout, traditionally known as polygon compactors, produces a design rule correct (DRC) version of a block from raw GDSII and a design-rule description. For a proper fit into a real-world design environment, more is needed than just fitting polygons onto minimum design-rule coordinates. This is achieved by layout migration, of which polygon compaction is only a part. Layout migration controls transistor sizes, power supplies, via-doubling and contact optimization.

Layout migration software is the optimal solution for hard IP reuse because it guarantees optimal design density by positioning each polygon-edge individually to optimum locations and enforcing the physical design rules. Since layout migration also involves exact control over each individual device size, it is also a perfect tool for manipulating transistor dimensions in the final layout to tune the design for performance and power consumption. Designs can be migrated and optimized using layout migration in combination with circuit optimization.

Hard IP optimization can also be a goal in itself, separate from migration.

Hard IP Optimization

For full-custom designs in an ultra deep submicron process, trying to estimate interconnect capacitances and the necessary device dimensions from a schematic design has become unfeasible for larger blocks. The reason is that since the final interconnect capacitances depend largely on the physical implementation, requiring device sizes to be modified even after layout has been drawn according to the specification.

As a result, many IP blocks are not optimized for performance, area, power consumption and yield. A hard IP optimization flow can improve speed and power characteristics. Objectives for optimization can be any combination of performance, power consumption, silicon area and manufacturability, depending on design specs and production volumes. The optimization can serve as a final step in the design of new IP, by fine-tuning each transistor for exact load. This fine tuning is also applicable in a reuse context, where new transistor dimensions may be chosen to make a migrated design fit requirements of the new manufacturing process.

The optimization source is always some form of hard IP, regardless of the way it was created –– full-custom design, place and route or migration, for example. Since the objective is to tune each transistor to its exact loading, a resistance/capacitance (RC)-extraction from the original hard IP is performed, which yields a SPICE file. The SPICE representation serves as input to a circuit optimization program that will determine new transistor width and length parameters, ensuring requirements are met. The circuit optimization is the part where most of the user-interaction takes place. In several optimization runs, a balanced tradeoff is found between required performance, power consumption and silicon area.

The compaction engine –– or the layout migration software –– is given the task to implement each of these new transistor sizes on the original design. For most transistors, this means they will be reduced in size, because a worst-case drive capability will have been used in the design. Some transistors will need to be enlarged –– such as devices on the critical path for delay time.

The optimization flow described below was used to design a 16-bit multiplier, implemented by a 10,005-transistor datapath-style, full-custom design in CMOS 0.25-m process.

Electronic Design Automation (EDA) software used included Amps and Arcadia developed by Synopsys and the Hurricane compaction softwarefrom Sagantec.

Delay-time was selected as the primary target. Bottom line results showed that delay could be improved by 11.7 percent at an area increase of only 2.6 percent. The target performance enhancement for Amps was defined to be a 10 percent gain compared to the original design. Results from Amps predicted a slightly better performance. All device sizes as specified by Amps were implemented correctly by Hurricane, leading to an optimized layout 2.6 percent larger than the original.

The final results:

Delay area free W -11.4% +11.0%

4/5 u W -11.7% + 2.6%

The "free W" run did not impose constraints on Amps for new target transistor widths. As a result, Amps selected only a few transistors for a substantial increase in W. These were transistors that could not possibly be grown to these new widths, most of them around 10-m , without serious impact on layout dimension. A second Amps run was performed, now limiting the maximum growth of a transistor width to 4-m for a nmos gate and 5-m for a pmos gate. Amps was now forced to increase more transistors in size, but only moderately.

This illustrates advantages of using a hard IP optimization flow. An improvement in speed was obtained without logic redesign and with only a minor increase in silicon area. The original design was leaving performance on the table, even though it was designed as a full-custom block to meet the high-performance criteria. Results after verification showed that the final performance after compaction was even slightly better then predicted by Amps.

A hard IP optimization design flow using circuit optimization and layout compaction software can optimize hard IP for performance and power consumption without a need for logic redesign. This optimization flow, used in conjunction with compaction, can significantly help in reducing the timing closure bottleneck of DSM-based designs.