*   Need to quickly migrate analog or custom IP to 40nm*?

*   Having hard time with 40nm design rules?

 

* or 45nm , or 32nm, or 28nm, or 65nm, or 55nm, or 90nm, or 80nm,

or any other technology

 

Let Sagantec handle these challenges for you.

 

Stop by the Sagantec booth # 1307 at DAC 2009 in San Francisco and talk with actual customers who use Sagantec products for layout productivity and process migration.

 

Check out how:

 

*      Mixed-signal IP designers migrated a 10Gbps Serdes from 65nm to 45nm technology (in 1/10 the time)

 

*      A silicon IP provider ported its high-performance mixed-signal IP to 3 (three) different 45/40nm foundries.

 

*      A leading fabless chip company uses Sagantec automatic DRC-fixing and compaction tools to boost custom layout productivity in 65nm and 40nm technology nodes. (Cadence CDNLive Award Winner!)

 

 

Register for one or more of the following demos:

 

*      Customer Demo

Analog/MS high-performance IP Migration to Advanced Processes

65nm to 45 Migration of high-performance Analog/MS circuit to advanced process technology. Maintaining hierarchy, Pcells, all Virtuoso objects, and all layout sensitive qualities like symmetry and matching.

 

*      Customer Demo

Porting custom circuits & designs between foundries

All at the 45/40nm technology node

 

*      Coping with complex and restrictive design rules in 40nm and beyond

 

*      Custom layout design Productivity in 65nm and 40nm

  • Automatic correction of DRC violations
  • Automatic DFM rule implementation
  • Updating foundry design-rule changes

           

*      Accelerated Analog Design Creation with Anaconda-M

  • Within Virtuoso Platform