·
Custom, analog and mixed-signal IP migration
·
Migration to latest technologies: 40, 32 and 28nm migration
·
Automatic PDK update, design rule changes, and DRC
correction
·
Standard cell library migration and optimization
Migration
of custom IP to next process node or different foundry
·
Supporting
all process technologies
·
Maintain
and enforce geometric constraints like symmetry, matching, alignments, etc.
·
Maintain original design hierarchy and structure
·
Support Cadence Virtuoso® IC5 and IC6
database
·
Support Pcells and all other Virtuoso data objects
Check out analog
IP migration success story
…………………………………………………………………………..
Sagantec
migration technology has been used and
proven down to 28nm
·
Overcoming topology
and device changes
·
Overcoming new
restrictive design rules
·
Used an proven on
multiple designs
Check out new 28nm migration success story article
……………….
·
PDK and design rule changes
Adjusting
layout to new PDK and design rule changes
·
Swap between
Pcells and PDKs
·
Update new design
rule values
·
Automatic
correction of DRC errors
·
Implement
recommended DFM rules without changing layout foot-print
·
For custom,
analog/ mixed-signal blocks and IP
·
For large digital
blocks and full chips
Check out new PDK adjustment success story article
………………….
…………….…..
……………
Migrate, modify and optimize standard cell libraries
in the most advanced technologies
·
Migrate libraries
to next technology node or between foundries
·
Supports topology
and routing changes (e.g. for 28nm and 22nm)
·
Create new
library derivatives (HS, LP, etc)
·
Analyze and
optimize libraries for yield
Process migration Change #tracks
