DFM-Fix is a tool that automatically optimizes design tape-out data to eliminate lithography related “hot spots,” providing designers with a shorter path to high yielding first silicon, greatly improving turnaround time and eliminating costly mask and wafer re-spins.
DFM-Fix is the first and only product that solves the lithography-related “hot spot” problem, at the root - by correcting the design data.
Today’s’ integrated circuit (IC) design implementation flows for 65nm and 45nm technologies are not completely aware of the manufacturing process variability and limitations. Post-design optical proximity correction (OPC) cannot guarantee pattern fidelity and “hot spot” free designs. IC manufacturers use post-OPC analysis and verification tools to detect these errors and try to correct them with multiple OPC iterations. This is a long and costly process, and there is no guarantee that all “hot spots” are fixed. The preferred solution is to optimize the design and to correct it before tape-out.
DFM-Fix uses information generated by post-OPC verification to initially identify the “hot-spots.” It then performs lithography analysis and evaluation of the original physical design at and around the location of the “hot-spots,” and uses advanced compaction technology to modify the design and correct it. DFM-Fix solves lithography related “hot-spots,” with minimal impact on the design and without violating any design rules.
At the core of the product is a hierarchical layout compaction and optimization engine developed on the basis of Sagantec’s SiFix. This layout optimization technology can make subtle polygon movements at minimum design-rule increments, and maintain design rule check (DRC) correctness while performing model-based optimization. The advantages of compaction compared to other methods is that it can move and size any wire and shape to any location and width while maintaining complete DRC correctness of all related polygons across all relevant layers. |
