|
Re-Use and Optimize your existing, silicon-proven intellectual property.
Sagantec's DREAM enables re-use of previously silicon-proven libraries for efficient and faster implementation of system on a chip.
Benefits
- Faster time-to-market for your standard-cell library, or custom cell library in your chosen new process
- Lower porting costs by migrating, rather than redesigning, cells and logic
- Leverage scarce circuit design and layout talent
- Start designing earlier and leverage the benefits of new process technology
- No change in existing design-verification environment
- Smaller silicon area as compared to traditional methods
- Squeeze more performance out of existing designs using the same process technology
Features
- Reads any GDS2 layout
- Produces DRC correct results in any DSM target technology
- Intelligent re-determination of wire lengths to optimize capacitance and signal delays
- Preservation of intercell abutment for pitch-matching
- Resolution of conflicts between process rules and user-specified constraints
- Prudent, controlled insertion of "doglegs" or jogs; no "reckless jogging"
- Transistor resizing, either automatically or from user-supplied directives
- Display of critical paths to identify overheight or overwidth cells
- Reproportioning of power-supply bus bars to satisfy electrical design rules
- Grid adherence for routing terminals to conform to router requirements
- Contact addition/deletion to optimize gates and well/substrate taps
- Includes DSM "preferred designrules", to optimize yield without increasing silicon area.
DREAM
DREAM is a design automation tool that enables rapid re-use and optimization of silicon-proven, standard cell libraries and custom
libraries, in new process
technologies. Re-using hard IP is an efficient and speedier method for developing a system on a chip while leveraging the previous investment in design. With DREAM, silicon-proven hard IP can be rapidly re-targeted to new processes and can take advantage of the latest deep submicron process to enhance the performance of existing or new products. It also can be used to retarget existing IC designs to develop a second source or to optimize a design for power and performance in existing process technologies.
 DREAM does a re-layout of the existing cell or block to new process design rules, and produces an optimized and design rule correct, new layout. DREAM preserves the source design's
functionality and layout topology. Since DREAM re-uses silicon-proven layout, it eliminates debugging concerns associated with redesign processes using synthesis, replace and re-routing.
Sagantec's DREAM is the industry's most widely used physical design migration tool. It has successfully migrated large numbers of standard cell and custom libraries.
The inputs to DREAM are a source
layout in GDS2 or CIF format and the new design rule file for target process technologies and any user-specified constraints. Based on these inputs, DREAM produces a new optimized layout in
GDS2/CIF format conforming to the new process design rules while preserving the functionality and maintaining the layout topology of the source layout. DREAM is a polygon compactor that
manipulates individual polygon edges by moving them closer together until constraints, either from a new process design rule file or from a user-specified constraint, are about to be violated.
DREAM's level of judgment and sophistication approaches that of a competent layout designer.
DREAM's many capabilities and expert rules, such as recontacting, direction control, wire length
minimization, automatic jog insertion, transistor resizing, and reproportioning of power-supply bus
bars, enable DREAM to generate a denser layout as compared to a traditional "linear shrink." DREAM consistently generates layouts that are 10 to 20 percent better than traditional linear
shrink. It can handle any kind of 45-degree layout.
Sagantec's DREAM design rule file is easy to set up, unlike other tools in the market. A typical
design rule file for DREAM can be created in a day as compared to weeks for competing products. Proven files for popular CMOS rules are supplied with DREAM to enable faster development of
customer-specific design rule files.
Sagantec's worldwide resources of experienced application engineers are always available to
provide support for rapid implementation of customers' design re-use projects. Most design migration projects can be completed in a few weeks with DREAM as compared to several months
with other methods.
DREAM's integration with industry standard timing and power optimization tools enables automated
transistor resizing for speed and power at the layout level. DREAM characterization and physical design verification tools enabling faster verification of migrated layouts.
DREAM for Standard Cell Library
Most independent, standard cell library suppliers use DREAM. A library of 400 standard cells can
be ported to a new process in less than two weeks by a competent layout person or integrated circuit designer using DREAM. Without DREAM, the same person may need six months to
complete the same task.
 With DREAM, designers can migrate an existing cell
library to meet new cell height requirements, new router gridding requirements, and new transistor sizes. All standard cells can be automatically pitch-matched to other
cells by specifying adjacency/abutment relations. An abutment relation between two cells will ensure that these two cells, including all contacts and layers on the edge,
will fit after compaction. DREAM can fit an existing cell library to a new template cell, or it can fit cells to an existing port specification. DREAM can put ports on a grid
to make the cells compatible with routers. DREAM's "preferred designrule" feature maximized the fabrication yield of resulting libraries, without increasing silicon area.
DREAM's integration with industry standard timing characterization and model generation tools
allow for faster verification of the migrated library. Since the library can be migrated and characterized quickly to a new process with DREAM and other tools, logic designers can start
designing early with this library and take advantage of the performance offered by the latest process technology.
Summary
Sagantec's DREAM enables re-use of silicon-proven, designs of standard cell libraries and custom
libraries to conform to the exact design rules of a desirable, newer, faster deep submicron process.
Results from DREAM are comparable to results from handcrafting, and are far superior to those from a traditional linear/optical shrink. DREAM applies sophisticated judgment factors to achieve
design rule correct layout in the new process. Each piece of logic is migrated to the new process,
rather than being simplistically shrunk. In general, design rules can be changed nonlinearly. A workstation or a group of interconnected workstations running DREAM can perform a compaction to
a new process in much less time than a human designer, thus shortening time to market. The compacted cells automatically come out design rule correct, and the same simulation and
test-vector suites that worked before the compaction can still be used. If the old layout was referred
to a grid, the new layout may likewise be referred to a revised grid. DREAM saves time, money, and person-power.
Platforms:
Sagantec tools run on Solaris 2.5/2.6/7/8, HP-UX 11.
Contact dream@sagantec.nl for compatibility with other tools, standards, or support of other hardware platforms.
|
