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Anaconda
Anaconda is a schematic-driven, constraint-based compaction tool that
accelerates analog physical design by automating repetitive manual layout
tasks and enabling analog design reuse. From an easy-to-use and powerful
graphical user interface, designers can add constraints in both schematic
and layout views thereby annotating the design database with design intent.
Anaconda then automatically updates the layout according to schematic device
parameters and additional design constraints to create a refined and final
DRC and LVS correct layout. SiFix
SiFix automatically detects and corrects physical violations in technology and reliability design rules, shortening implementation time and improving manufacturing yield. SiFix speeds physical designs that use highly complex design rules associated with advanced process technologies of 0.13 um and below. Hurricane
Hurricane
is high capacity, high speed software to accelerate system-on-chip
implementation. Hurricane is used to optimize and migrate large physical IP cores to new process technologies. The physical design migration software leverages Sagantec's expertise in hard IP reuse for deep submicron technologies. Hurricane migrates large layouts quickly creating denser and more compact layout, and can
optimize transistor sizes and wire widths. SiClone
SiClone is a native hierarchical compaction technology that provides complete hierarchy preservation during physical design compaction and migration.
SiClone accelerates physical implementation and closure for full-custom design. It enables simultaneous, n-level hierarchical layout compaction, process migration and physical optimization. Companion
Companion works seamlessly with the
Virtuoso®
layout editor from Cadence Design Systems for rapid cell and IP development to accelerate custom design process and to significantly
reduce the number of DRC and LVS iterations. A layout engineer does a rough, preliminary place and route with Virtuoso and then uses the 'compact' button on the Virtuoso tool bar. Companion examines the layout, repositions the polygons to fix DRC errors, places all edges on grid and further compacts the layout to render the placement and routing into a correct and optimized detailed physical design. XTREME
XTREME solves difficult physical design issues that are introduced with the advent of deep submicron process technologies. XTREME re-engineers chip interconnect wires to significantly reduce coupling capacitance and crosstalk, reduces critical net loads, and enhances signal integrity, overall reliability and yield. XTREME can operate on all routing levels and maintains the physical design hierarchy and structure. Supported Platformss
- Sun Sparc (Solaris), HP (HP-UX) and Linux
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