Significantly reduces crosstalk, enhances signal integrity, and improves yield in deep submicron physical design by re-engineering interconnect layout

Benefits

• Reduces coupling capacitance and crosstalk
• Increases manufacturing yield and reliability
• Enhances signal integrity
• Reduces power consumption
• Improves performance

Features

• User defined, net specific or globally spaces and widens interconnect
• Handles any number of interconnect layers
• Supports a variety of routing styles
• Preserves hierarchy and connectivity
• Interfaces with industry standard place and route tools using LEF/DEF
• Accepts shape and symbolic data
• User controlled option for automatically doubling of vias
• Provides full control of spacing and width tradeoff
• Handles large million-gate designs