In advanced process technologies the number and complexity of design rules is overwhelming. Current layout tools cannot create efficient layout that is also DRC correct without extensive manual intervention, and the layout designers themselves find it hard and extremely time consuming to deal with the amount and complexity of these design rules.

Furthermore, the dynamics of semiconductor advanced processes are such that the design rules themselves keep changing, reflecting the process yield ramp curve. This makes design rules and process design kits (PDKs) a moving target thatís hard for designers to follow. With automatic layout correction, this dynamics does not hinder design schedule, as designers can start their design early on with an early version of the design rule manual, and then perform instant updates every time rules or PDKs change.

Recommended (or DFM) design rules are yet another new challenge for designers. As their name suggests, they are not mandatory, yet they have a significant impact on yield. Implementing all of them indiscriminately will result in severe penalties to both design schedule and silicon area. With automatic DFM rule implementation, recommended rules are implemented in an optimal manner, with no area penalty and according to pre-defined rule criticalities and priorities.

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