Anaconda™ Squeezes More Productivity from Existing Analog Design Flow

Sagantec’s Anaconda is a powerful and practical schematic-driven solution that accelerates repetitive manual layout tasks and enables analog design reuse

FREMONT, Calif., May 19, 2003 - Sagantec today announced Anaconda, a schematic-driven, constraint-based compaction tool that accelerates analog physical design by automating repetitive manual layout tasks and enabling analog design reuse.

Anaconda is the first analog design product to target the significant manual effort involved in analog reuse today—from the effort required to correctly place and size the layout details of the many derivatives and variations of a given physical topology to the migration of circuits to new processes. In sum, these activities consume an overwhelming amount of physical design time—much more than initial topology creation. An automated alternative to hand-layout of each derivative, Anaconda reads sizes and constraints from a schematic and then refines a given topology to automatically and accurately implement the specifications, resulting in a correct and complete layout.

"Analog sections of a chip may be small, but the impact they have on the chip’s overall design schedule is significant,” explains Coby Zelnik, senior vice president of business development at Sagantec. “Our customers tell us that the biggest productivity drain felt now in analog design is in the tedious refinement of the layout details after a topology has already been created. In fact, they see their analog design productivity issue as one that can be resolved through faster, easier reuse of existing physical topology. Anaconda addresses exactly these areas. The beauty of this solution is that it is schematic-driven and easily fits into their existing methodologies and design flows."

Anaconda Approach

Anaconda’s precise and intelligent geometry compaction engine reads device parameters and topology constraints from schematics and executes automatically, deciding all geometric details for correct-by-construction device placement and sizing. Anaconda checks and guarantees symmetry, wire widths, matching, alignment, and correct design rules. Anaconda’s geometry engine and database incorporate expertise gained over Sagantec’s years of migrating complex analog layouts. Anaconda is seamlessly integrated with Cadence’s schematic-driven Virtuoso XL design system. With Anaconda, designers remain in full control. They can drive incremental engineering change orders (ECOs) from the schematic and can make topology changes using the Virtuoso layout editor.

Pricing and Availability

Anaconda is available in Q3 2003 under time-based licensing starting at $55,000 a year. Anaconda is available on Solaris, HP-UX and Linux platforms and is compatible with Cadence Virtuoso 4.4.x

About Sagantec

The leader in layout acceleration, process migration and compaction, Sagantec develops software and solutions enabling reuse of full-custom design, including analog mixed-signal circuits. Sagantec solutions are used to migrate designs to either the newest technology or to a different process at the same technology node. Privately held and funded, Sagantec was founded in 1993 in Israel. Its corporate headquarters is located at 2075 De La Cruz Blvd, Suite #105, Santa Clara, CA. 95050. Telephone: (408) 727-6290. Facsimile: (408) 727-6288. On the web at: http://www.sagantec.com.

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For more information, contact:
Phyllis Orlando
Sagantec
Tel: 408.727.6290
Email: phyllis@sagantec.com