Sagantec provides the missing link to a complete DFM solution

Enables design modification and optimization for lithography-correct design.

FREMONT, Calif., June 26, 2006 Sagantec has announced DFM-Fixä, a tool that automatically optimizes design tape-out data to eliminate lithography related “hot spots.” This will provide designers with a shorter path to high-yielding first silicon, greatly improving turnaround time and eliminating costly mask and wafer re-spins.

DFM-Fix is the first and only announced product that solves the lithography-related “hot spot” problem at the design data stage.

Today’s integrated circuit (IC) design implementation flows for 65nm and 45nm technologies are not completely aware of the manufacturing process variability and limitations. Post-design optical proximity correction (OPC) cannot guarantee pattern fidelity and “hot spot” free designs. IC manufacturers use post-OPC analysis and verification tools to detect these errors and try to correct them with multiple OPC iterations. This is a long and costly process, and there is no guarantee that all “hot spots” are fixed. The preferred solution is to optimize the design and to correct it before tape-out.

While there have been a few recent announcements of new products that attempt to bring some lithography and manufacturing analysis capabilities into the design stage, what has been lacking is a physical design optimization tool that can consider analysis results and automatically make the proper changes to a layout without introducing new violations. DFM-Fix fills this critical missing link that is needed for a complete design for manufacturability (DFM) flow.

Sagantec is the established leader in process migration technology. This technology provides powerful and flexible functionality to fix and optimize layouts. Enhancing this technology with both advanced rule-based optimization and model-based capabilities has created DFM-Fix, the only viable solution today for DFM layout optimization.

“Sagantec believes that IC design implementation needs to be litho-optimized and correct before tape-out,” said Hillel Ofek, president and chief executive officer at Sagantec. “A complete solution must include a layout correction and optimization technology. Sagantec’s technology is silicon proven at 65nm, and is already used for 45nm design implementation. It is mature, robust, and best suited to fulfill these critical tasks.”

DFM-Fix optimizes and corrects physical designs to eliminate lithography related “hot-spots.” This tool uses information generated by third-party post-OPC verification tools to initially identify the “hot-spots.” It then performs lithography analysis and evaluation of the original physical design at and around the location of the “hot-spots,” and uses advanced compaction technology to modify the design and correct it. DFM-Fix is focused on solving lithography related “hot-spots,” and doing so with minimal impact on the design and without violating any design rules.

At the core of the product is a hierarchical layout compaction and optimization engine that was developed on the basis of Sagantec’s SiFix product. This layout optimization technology can make subtle polygon movements at minimum design-rule increments, and maintain design rule check (DRC) correctness while performing model-based optimization. The advantages of compaction compared to other methods is that it can move and size any wire and shape to any location and width while maintaining complete DRC correctness of all related polygons across all relevant layers. Users can guide and control the tool’s operation and limit the modification to specific layers, cell names, and/or levels of hierarchy.

Semiconductor companies have commercially used the base compaction technology of SiFix for more than 5 years for rule-based process migration and design-rule correction. During its commercial use spanning 5 technology generations from 180nm to 45nm, the technology has been constantly enhanced and updated and has already delivered 65nm silicon and tape-out quality 45nm layout of leading-edge IC designs.

DFM-Fix is a part of Sagantec’s DFM product strategy, which is centered on its silicon proven optimization technology. This product will be unveiled at the Design Automation Conference (DAC) in San Francisco in July 2006, and will be available in late 2006.

About Sagantec

Sagantec accelerates design to silicon in advanced process technologies. Sagantec’s EDA products enable a dramatic shortcut in the successful deployment of new silicon technology through the use of physical design reuse, automatic process migration and DFM optimization. Sagantec's migration tools are used to redirect designs to either the newest technology or to a different process at the same technology node. Sagantec's DFM solutions accelerate delivery of high-yielding silicon through physical-design optimization. Privately held and funded, its corporate headquarters is at 46485 Landing Parkway, Fremont, CA. 94538. Telephone: (510) 360-5200. Facsimile: (510) 360-5255. On the Web at: www.sagantec.com

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