Sagantec Speeds Porting of High-Performance Interface IP at MoSys

Santa Clara, California – July 15 , 2009 – Sagantec today announced that MoSys Inc., a leading provider of multi-protocol SerDes and DDR3 IP, has deployed Sagantec’s Anaconda-M solution as part of it’s methodology for automating and accelerating its process porting flow. The Anaconda-M solution was successfully used by MoSys to help migrate its high-performance interface IP designs from 65 nanometer to 45/40 nanometer technology.

The Anaconda-M based solution has facilitated significant productivity gains compared with traditional design methods, and has enabled MoSys to shorten design schedules and very quickly generate multiple process implementations with limited resources. The first one of these implementations is already silicon proven.

“MoSys delivers high-performance interface IP in the most advanced process technologies. Implementing such IP with various foundries and multiple technology nodes is a significant resource and time challenge” said Ritesh Saraf, MoSys’ Vice President of Silicon Engineering. “We needed a reliable solution to handle all aspects of the physical design migration quickly and efficiently while at the same time maintaining the integrity and quality of our original implementation. Anaconda-M did exactly that and has helped us to significantly shorten our porting schedules.”

“We are very pleased that MoSys has chosen Sagantec as a critical component of their IP implementation porting solution. Their cutting-edge designs, strong feature requirements and productivity goals make for a high-standard benchmark for any design automation technology in the analog/mixed-signal space,” said Coby Zelnik, Sagantec’s President and CEO. “High-performance custom IPs are becoming increasingly critical components in today’s IC designs. Sagantec’s Anaconda-M provides easier and faster portability of such IPs and enables their on-time availability for any advanced process node and across multiple fabrication sources.”

About Anaconda-M

Anaconda-M is a physical design migration and optimization tool for analog/mixed-signal IP. It automates and accelerates the design migration process of large custom and analog and mixed-signal silicon IP. Anaconda-M preserves the design intent, hierarchy structure and topology, as well as geometry-sensitive layout properties, such as matching and symmetry. Anaconda-M can be used from within Cadence Design System’s Virtuoso custom design platform and can be driven from both schematic and layout views. Anaconda-M is used to migrate IP designs from one technology to the next or port designs across different foundry processes. It can automatically adjust and physically implement circuit properties such as devices sizes, as well as routing constraints such as widths, spacing, etc. Anaconda-M cuts significant time not only in initial re-implementation, but also in implementing ECOs, design-rule changes, EM rules, DFM rules, etc. Anaconda-M has seamless integration into the Cadence Virtuoso platform, supporting both IC 5 and IC 6 versions and maintaining Pcell and connectivity information.

About MoSys, Inc.
Founded in 1991, MoSys develops, markets and licenses innovative embedded memory and high performance parallel and serial interface intellectual property (IP) technologies for advanced systems-on-chips (SoCs) used in a variety of home entertainment, mobile consumer, networking and storage applications. MoSys' patented 1T-SRAM and 1T-FLASH technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. MoSys' embedded memory IP has been included in more than 175 million devices demonstrating silicon-proven manufacturability in a wide range of processes and applications. MoSys’s silicon proven interface IP portfolio includes DDR3/2 Combo PHYs as well as SerDes IP supporting data rates from SGMII (1.25Gbps) to 10G KR and CEI-11. These also include XAUI (3.125Gbps and 6.25Gbps), USB 3.0 (5Gbps), PCI Express Gen1 (2.5Gbps) and Gen2 (5.0Gbps), SATA I, II and III. MoSys is headquartered at 755 N. Mathilda Avenue, Sunnyvale, California 94085. More information is available on MoSys' website at and

About Sagantec
Sagantec accelerates delivery of physical silicon IP in advanced process technologies. Sagantec’s electronic design automation solutions enable a dramatic shortcut in the successful deployment of new silicon technology through the use of physical design reuse, automatic process migration and DFM optimization. Sagantec's process migration tools are used to redirect designs to either the next technology node or to a different process at the same or previous technology node. For analog and mixed-signal IP designers, Sagantec enables the fastest migration path to 65nm, 45nm and 32nm process technologies. Privately held and funded, its corporate headquarters is at 2075 De La Cruz Blvd., Santa Clara, CA 95050. Telephone: (408) 727-6290. Facsimile: (408) 727-6288. On the Web at:


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